There have been prototype implementations of an early version of the standard. These implementations were done by Agilent Technologies Inc. (then part of Hewlett-Packard Inc.). While these early implementations are not conformant to the final version of IEEE 1588, the performance of these prototypes gives a good indication of what can be expected. The main differences between the prototype implementations and the final version of the standard are in the details of the message formats, and incomplete implementation of features added during the standardization process. Agilent implemented three prototypes, two using Ethernet and one using LonTalkTM. One, discussed here, was an ASIC implementation, the other two utilized an FPGA for the clock and synchronization hardware and a microprocessor for the computations. Published references to this work are found here. All data reported here is courtesy of Agilent Technologies.
Figure 1 below illustrates the test environment used to characterize the performance of the prototypes. The ASIC shown in the picture contains a microprocessor, an Ethernet MAC, and the hardware assist referenced in IEEE 1588 and the 1588 clock. The microprocessor, roughly equivalent to a 40MHz 68020, executes the synchronization protocol as well as the applications for which the ASIC was designed. The synchronization code requires about 7K of flash and minimal usage of RAM. The crystal oscillator used to drive the clock and the microprocessor is an inexpensive 40MHz device, Kinseki FXO-31F. The resolution of the clock is 25ns. The two clocks communicate via Ethernet using one or more repeaters or switches. Each clock also provides a 1 pulse per second signal on the seconds boundary of the clock. These 1 PPS signals are captured and analyzed by the Agilent Technologies 5372A Frequency and Time Analyzer to produce the data reported below. In each case the figures illustrate 1 hours worth (3600 points) of data.
Figure 1: Experimental Setup
Figure 2 illustrates the performance when the master clock and the slave clock are separated by a single Hewlett-Packard J4090A repeater. The repeater was connected to the building LAN environment via a single Hewlett-Packard J4121A switch. Therefore at a minimum the repeater experienced all of the normal building multicast traffic, ARP etc. The deviations between the 1 PPS signals of each of the clocks are shown on the histogram. The computed standard deviation is 73ns and the mean is 32ns. The maximum and minimum deviations of the 1 PPS signals are +256ns and -163ns respectively. The protocol automatically corrects for a mean delay of approximately 1664ns through the network, repeater, and the relevant portions of the clock's operating system protocol stack. The synchronization is accomplished with one measurement and one reporting packet on the network in each 2 second interval (~1 packet/second 1588 network traffic) as specified in IEEE 1588.
Figure 2: Histogram 1 PPS offsets for two Agilent prototype clocks communicating via a single HP J4090A Ethernet repeater
Figure 3 illustrates the performance when the master clock and the slave clock are separated by a single Hewlett-Packard J4121A switch. The switch was connected to the building LAN environment via a second Hewlett-Packard J4121A switch. Therefore at a minimum the switch experienced all of the normal building multicast traffic, ARP etc. The deviations between the 1 PPS signals of each of the clocks are shown on the histogram. The computed standard deviation is 147ns and the mean is -24ns. The maximum and minimum deviations of the 1 PPS signals are +441ns and -458ns respectively. The protocol automatically corrects for a mean delay of approximately 121834ns through the network, switch, and the relevant portions of the clock's operating system protocol stack.
Figure 3: Histogram 1 PPS offsets for two Agilent prototype clocks communicating via a single HP J4121A Ethernet switch
A summary of the data for the repeater and switch cases is shown in the following table:
| Measured Quantity | Repeater Data | Switch Data |
|---|---|---|
| Mean Offset Deviation-ns | 32 | -24 |
| Standard Deviation of Offset-ns | 73 | 147 |
| Maximum Deviation of Offset-ns | 256 | 441 |
| Minimum Deviation of Offset-ns | -163 | -458 |
| Latency Removed by Protocol-ns | 1554 | 121834 |
The switch clearly increases the standard deviation and the extremes. In both cases the protocol successfully removed the very large latency introduced by the repeater and switch. In the case of the switch a detailed study of the actual data used in the correction computation of the slave clock shows that with the switch, but not the repeater, there are occasional computed corrections well outside the normal values. The prototype implemented a simple algorithm that discards these outliers yielding the results given here. Without this algorithm the results for the switch case would be degraded. These outliers are thought to arise from occasional queuing delays in the switch due to other traffic. When using the J4121A switch as described these outliers occur perhaps once or twice an hour under the traffic present in our lab. When disconnected from the lab LAN the outliers disappeared. As noted in the discussion on switches, it is possible to design switches that completely remove this problem.